IBM Unveils Sub 1 nm Nanostack Chip Tech With Massive Performance Gains

IBM has unveiled a new nanostack transistor architecture that it describes as the world’s first sub 1 nanometer chip technology, capable of fitting nearly 100 billion transistors on a fingernail sized chip. The design vertically stacks transistors to overcome physical scaling limits, delivering performance gains equivalent to a theoretical 0.7 nm node. IBM projects up to 50 percent higher compute performance or 70 percent better energy efficiency compared to its 2 nm generation. The architecture also enables a 40 percent improvement in SRAM scaling, a major bottleneck for AI workloads. While IBM does not manufacture chips itself, it expects commercial partners to adopt the technology within five to ten years, potentially making nanostack the next mainstream transistor architecture.

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